Two important elements in a computer system are the processor and the memory. The processor operates on data stored in the memory and generally controls the transfer of data into and out of the memory. Other elements of the computer system may also require access to the memory. In order to avoid conflicts such as overlapping requests for memory access, the processor typically controls access to the memory by arbitrating between the various requests.
As the computer system becomes more complex, an increasing number of elements require access to the memory. For example, multiple processors and control units in a computer system require individual access to the memory. Although multiple processors and control units can provide increased efficiency, speed and functionality, they also crate a memory access bottleneck. This can result in more wait states for each element which can deteriorate system performance.
Another factor contributing to memory access delays is related to the use of the data bus interconnecting the various elements and the memory. The data bus is used for data transfers between the various elements as well as for memory access. Since simultaneous use of the bus is not permitted, an element may have to wait for access to the bus as well as having to wait for access to the memory. In other words, if all the elements of a system are connected to the same bus there is competition not only to access the memory but also to have access to the bus.
In order to reduce the bus contention problems, multiple busses with fewer elements connected to each bus may be employed. This will reduce bus contention problems and allow different bus activities to occur simultaneously without mutual interference. However, if a single memory is to be maintained, access to the memory still involves delays.
A dual port memory design allows access of a single memory from two busses. A typical dual port memory design is shown in U.S. Pat. No. 4,796,232. The '232 design provides access to a multiple bank, DRAM memory through two ports. A logic circuit arbitrates between read/write requests from the ports and DRAM refresh requests. The logic circuit allows one memory bank to be refreshed while another bank is accessed by a read or write to a port. The '232 design also uses a data register between each bus and the memory banks. A data register will accept, for example, a data element written from a bus thereby freeing that bus for other activity. However, subsequent data elements can not be written from that bus until the data element in the register is written into memory. The transfer of the data element from the register into memory may involve some delays because it must compete with transfer requests from the other bus and with refresh requests.